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Year 2025, Volume: 12 Issue: 1, 61 - 71, 26.03.2025

Ahmet Unutulmaz

https://doi.org/10.54287/gujsa.1645022

Abstract

References

  • Celinski, P., López, J. F., Al-Sarawi, S., & Abbott, D. (2002). Compact parallel (m, n) counters based on self-timed threshold logic. Electronics Letters, 38(13), 633-635. https://doi.org/10.1049/el:20020438
  • Han, J. K., Lee, M. W., Yu, J. M., & Choi, Y. K. (2021). A Single Transistor‐Based Threshold Switch for a Bio‐Inspired Reconfigurable Threshold Logic. Advanced Electronic Materials, 7(5), 2100117. https://doi.org/10.1002/aelm.202100117
  • Kulkarni, N., Yang, J., Seo, J. S., & Vrudhula, S. (2016). Reducing power, leakage, and area of standard-cell asics using threshold logic flip-flops. IEEE Transactions on very large scale integration (VLSI) systems, 24(9), 2873-2886. https://doi.org/10.1109/tvlsi.2016.2527783
  • Maan, A. K., Jayadevi, D. A. & James A. P., (2016). A survey of memristive threshold logic circuits. IEEE Transactions on Neural Networks and Learning Systems, 28(8), 1734–1746. https://doi.org/10.1109/tnnls.2016.2547842
  • Mazumder, P., Kang, S.-M. & Waser, R. (2012). Memristors: Devices, Models and Applications. In: Proceedings of IEEE, 100 (6), (pp. 1911–1919). https://doi.org/10.1109/JPROC.2012.2190812
  • Papandroulidakis, G., Serb, A., Khiat, A., Merrett, G. V. & Prodromakis, T. (2019). Practical implementation of memristor-based threshold logic gates. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(8), 3041–3051. https://doi.org/10.1109/TCSI.2019.2902475
  • Sarkar, M., Chakraborty, R., Taki, G. S., & Chakraborty, A. K. (2021). Design of basic logic gates using optical threshold logic. Engineering Research Express, 3(3), 035021. https://doi.org/10.1088/2631-8695/ac1903
  • Saxena, P., Shelar, R. S., & Sapatnekar, S. (2007). Routing Congestion in VLSI Circuits: Estimation and Optimization. Springer Science & Business Media. https://doi.org/10.1007/0-387-48550-3
  • Unutulmaz, A., & Ünsalan, C. (2024). Implementation and applications of a ternary threshold logic gate. Circuits, Systems, and Signal Processing, 43(2), 1192-1207. https://doi.org/10.1007/s00034-023-02512-1
  • Vrudhula, S., Kulkami, N. & Yang, J. (2015). Design of threshold logic gates using emerging devices. In: Proceedings of 2015 IEEE International Symposium on Circuits and Systems, Lisbon, (pp 373–376). https://doi.org/10.1109/iscas. 2015.7168648
  • Wagle, A., & Vrudhula. S. (2021) Heterogeneous FPGA architecture using threshold logic gates for improved area, power, and performance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(6), 1855-1867. https://doi.org/10.1109/TCAD.2021.3099780
  • Yang, J., Kulkarni, N., Yu, S. & Vrudhula, S. (2014). Integration of threshold logic gates with RRAM devices for energy efficient and robust operation, In: Proceedings of 2014 IEEE/ACM International Symposium on Nanoscale Architectures, (pp 39–44).
  • Youn, S., Lee, J., Kim, S., Park, J., Kim, K., & Kim, H. (2024). Programmable threshold logic implementations in a memristor crossbar array. Nano Letters, 24(12), 3581-3589. https://doi.org/10.1021/acs.nanolett.3c04073
  • Zhao, W., & Cao, Y. (2006). New generation of predictive technology model for sub-45 nm early design exploration. IEEE Transactions on electron Devices, 53(11), 2816-2823. https://doi.org/10.1109/ted.2006.884077

A Novel Dynamic Clock Generator Circuit for the Threshold Logic Gate

Year 2025, Volume: 12 Issue: 1, 61 - 71, 26.03.2025

Ahmet Unutulmaz

https://doi.org/10.54287/gujsa.1645022

Abstract

Threshold Logic Gate (TLG) has gained attention with the emergence of novel technologies such as memristors. TLG offers improved performance and lower power dissipation while occupying less silicon area. This paper introduces a novel dynamic clock generator circuit that further enhances TLG performance. The proposed circuit replaces the NAND gate-based approach used for clock generation in differential TLG implementations. It reduces the propagation delay of the TLG while reducing its static power dissipation, an important factor in energy-efficient circuit design. Simulations indicate up to a 25% reduction in delay compared to the NAND gate-based approach. Furthermore, the proposed circuit occupies 45% less area than the NAND gate. These findings highlight the potential of the proposed dynamic clock generator for advanced threshold logic implementations, paving the way for further innovations in the field.

Keywords

Threshold Logic Gate Dynamic Circuit Clock Generator

References

  • Celinski, P., López, J. F., Al-Sarawi, S., & Abbott, D. (2002). Compact parallel (m, n) counters based on self-timed threshold logic. Electronics Letters, 38(13), 633-635. https://doi.org/10.1049/el:20020438
  • Han, J. K., Lee, M. W., Yu, J. M., & Choi, Y. K. (2021). A Single Transistor‐Based Threshold Switch for a Bio‐Inspired Reconfigurable Threshold Logic. Advanced Electronic Materials, 7(5), 2100117. https://doi.org/10.1002/aelm.202100117
  • Kulkarni, N., Yang, J., Seo, J. S., & Vrudhula, S. (2016). Reducing power, leakage, and area of standard-cell asics using threshold logic flip-flops. IEEE Transactions on very large scale integration (VLSI) systems, 24(9), 2873-2886. https://doi.org/10.1109/tvlsi.2016.2527783
  • Maan, A. K., Jayadevi, D. A. & James A. P., (2016). A survey of memristive threshold logic circuits. IEEE Transactions on Neural Networks and Learning Systems, 28(8), 1734–1746. https://doi.org/10.1109/tnnls.2016.2547842
  • Mazumder, P., Kang, S.-M. & Waser, R. (2012). Memristors: Devices, Models and Applications. In: Proceedings of IEEE, 100 (6), (pp. 1911–1919). https://doi.org/10.1109/JPROC.2012.2190812
  • Papandroulidakis, G., Serb, A., Khiat, A., Merrett, G. V. & Prodromakis, T. (2019). Practical implementation of memristor-based threshold logic gates. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(8), 3041–3051. https://doi.org/10.1109/TCSI.2019.2902475
  • Sarkar, M., Chakraborty, R., Taki, G. S., & Chakraborty, A. K. (2021). Design of basic logic gates using optical threshold logic. Engineering Research Express, 3(3), 035021. https://doi.org/10.1088/2631-8695/ac1903
  • Saxena, P., Shelar, R. S., & Sapatnekar, S. (2007). Routing Congestion in VLSI Circuits: Estimation and Optimization. Springer Science & Business Media. https://doi.org/10.1007/0-387-48550-3
  • Unutulmaz, A., & Ünsalan, C. (2024). Implementation and applications of a ternary threshold logic gate. Circuits, Systems, and Signal Processing, 43(2), 1192-1207. https://doi.org/10.1007/s00034-023-02512-1
  • Vrudhula, S., Kulkami, N. & Yang, J. (2015). Design of threshold logic gates using emerging devices. In: Proceedings of 2015 IEEE International Symposium on Circuits and Systems, Lisbon, (pp 373–376). https://doi.org/10.1109/iscas. 2015.7168648
  • Wagle, A., & Vrudhula. S. (2021) Heterogeneous FPGA architecture using threshold logic gates for improved area, power, and performance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(6), 1855-1867. https://doi.org/10.1109/TCAD.2021.3099780
  • Yang, J., Kulkarni, N., Yu, S. & Vrudhula, S. (2014). Integration of threshold logic gates with RRAM devices for energy efficient and robust operation, In: Proceedings of 2014 IEEE/ACM International Symposium on Nanoscale Architectures, (pp 39–44).
  • Youn, S., Lee, J., Kim, S., Park, J., Kim, K., & Kim, H. (2024). Programmable threshold logic implementations in a memristor crossbar array. Nano Letters, 24(12), 3581-3589. https://doi.org/10.1021/acs.nanolett.3c04073
  • Zhao, W., & Cao, Y. (2006). New generation of predictive technology model for sub-45 nm early design exploration. IEEE Transactions on electron Devices, 53(11), 2816-2823. https://doi.org/10.1109/ted.2006.884077
There are 14 citations in total.

Details

Primary Language English
Subjects Digital Electronic Devices
Journal Section Electronics, Sensors and Digital Hardware
Authors

Ahmet Unutulmaz 0000-0001-7738-9286

Publication Date March 26, 2025
Submission Date February 23, 2025
Acceptance Date March 12, 2025
Published in Issue Year 2025 Volume: 12 Issue: 1

Cite

APA Unutulmaz, A. (2025). A Novel Dynamic Clock Generator Circuit for the Threshold Logic Gate. Gazi University Journal of Science Part A: Engineering and Innovation, 12(1), 61-71. https://doi.org/10.54287/gujsa.1645022
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